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1 zl1505 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. copyright intersil americas inc. 2009, 2010. all rights reserved. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a trademark owned by in tersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. synchronous step-down mosfet drivers zl1505 the zl1505 is an integrated high-speed, high-current n-channel mosfet driver for synchronous step-down dc/dc conversion applications. when used with zilker labs digital-dc? pwm controllers, the zl1505 enables dynamically adaptive dead-time control that optimizes efficiency under all operating conditions. a dual input pwm configuration enables this efficiency optimization while minimizing complexity within the driver. operating from a 4.5v to 7.5v input, the zl1505 combines a 5a, 0.5w low-side driver and a 3a, 0.8w high-side driver to support high step-down buck applications. a unique adjustable gate drive current scheme allows the user to adjust the drive current on both drivers to optimize performance for a wide rage of input/output voltages, load currents, power mosfets and switching frequencies up to 1.4mhz. an integrated 30v bootstrap schottky diode is used to charge the external bootstrap capacitor. an internal watchdog circuit prevents excessive shoot-through currents and protects the external mosfet switches. the zl1505 is specified over a wide -40c to +125c junction temperature range and is available in an exposed pad dfn-10 package. features ? high-speed, high-current drivers for synchronous n-channel mosfets ? adaptive dead-time control optimizes efficiency when used with digital-dc controllers ? integrated 30v bootstrap schottky diode ? capable of driving 40a per phase ? supports switching frequency up to 1.4mhz - >4a source, >5a sink low-side driver - >3a source/sink high-side driver - <10ns rise/fall times, low propagation delay ? adjustable gate drive strength optimizes efficiency for different v in , v out , i out , f sw and mosfet combinations ? internal non-overlap watchdog prevents shoot-through currents applications* (see page 12) ? high efficiency, high-current dc/dc buck converters with digital control and pmbus? ? multi-phase digital dc/dc converters with phase adding/dropping ?power train modules ? synchronous rectification for secondary side isolated power converters related literature* (see page 12) ? fn6846 zl2004 adaptive digital dc/dc controller with current sharing vdd bst gh sw zl1505 gl level shift shoot- through protection pwmh pwml gnd vdd lsel hsel figure 1. zl1505 block diagram november 12, 2010 fn6845.2
2 fn6845.2 november 12, 2010 typical application circuit the following application circuit represents the typi cal implementation of the zl1505 (notes 1, 2). notes: 1. for v dd of 4.5v to 7.5v, the maximum v in of the zl1505 is 22.5v to 25.5v. zl1505 input supply voltage range (v in ) is specified in figure 2. 2. v in for this application circuit is limited by the zl2004 v in of 4.5v to 14v. vout v in 4.5-14v v bias 4.5-7.5v zl2004 gnd gnd pwml pwmh pwml pwmh cs- cs+ temp- temp+ isenb isena vse n+ vse n- xtemp sgnd vin pwm h pwm l vdd bs t gnd gh gl sw zl1505 vin vdd power train module hs el lsel vmon figure 2. power train module using zl2004 pwm controller zl1505
3 fn6845.2 november 12, 2010 pin configuration zl1505 (10 ld dfn) top view pin descriptions pin number pin name type (note 3) description 1 hsel i high-side gate drive current sele ctor. connect to bst for maximum gate drive current; connect to sw for 50% of maximum gate drive current. 2 gh o output of high-side gate driver. connect to the gate of high-side fet. 3 sw i/o phase node. return path for high-sid e driver. connect to source of high-side fet and drain of low-side fet. 4 pwmh i high-side pwm control input. 5 pwml i low-side pwm control input. 6 lsel i low-side gate drive current sele ctor. connect to vdd for maximum gate drive current; connect to gnd for 50 % of maximum gate drive current. 7 gnd pwr ground. all signals return to this pin. 8 gl o output of low-side gate driver. connect to the gate of low-side fet. 9 vdd pwr gate drive bias supply. connect a hi gh quality bypass capacitor from this pin to gnd. 10 bst pwr bootstrap supply. connect external capacitor to sw node. epad gnd pwr ground. note: 3. i = input, o = output, pwr = power or ground. 2 3 4 1 5 9 8 7 10 6 hsel gh sw pwmh pwml bst vdd gl gnd lsel *connect to gnd *epad ordering information part number (notes 4, 5, 6) part marking temp range (c) package tape and reel (pb-free) pkg. dwg. # zl1505alnnt 1505 -40 to +125 10 ld 3x3 dfn l10.3x3d ZL1505ALNNT1 1505 -40 to +125 10 ld 3x3 dfn l10.3x3d zl1505alnnt6 1505 -40 to +125 10 ld 3x3 dfn l10.3x3d notes: 4. please refer to tb347 for details on reel specifications. 5. these intersil pb-free plastic packaged products employ special pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 terminat ion finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free produc ts are msl classified at pb -free peak reflow temperatur es that meet or exceed the pb-free requirements of ipc/jedec j std-020. 6. for moisture sensitivity level (msl), please see device in formation page for zl1505 . for more information on msl please see techbrief tb363 . zl1505
4 fn6845.2 november 12, 2010 absolute maximum ratings thermal information voltage measured with respect to gnd dc supply voltage for vdd pin . . . . . . . . . . . . . -0.3v to 8v high-side supply voltage for bst pin . . . . . . . . -0.3v to 30v high-side drive voltage for gh pin . . . . . . . . . . . . . . . (v sw - 0.3v) to (v bst + 0.3v) low-side drive voltage for gl pin . . . . . . . . . . . . . . . .(gnd - 0.3v) to (v dd + 0.3v) boost to switch differential (v bst - v sw ) for bst, sw pins . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 8v switch voltage for sw pin continuous . . . . . . . . . . . . . . . . . . . (gnd - 0.3v) to 30v <100ns . . . . . . . . . . . . . . . . . . . . . . . (gnd - 5v) to 30v logic i/o voltage for pwmh, pwml, lsel pins . . . -0.3v to 8v hsel pin . . . . . . . . . . . . . (v sw - 0.3v) to (v bst + 0.3v) esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . 2kv gl pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . 500v latch up . . . . . . . . . . . . . . . . . . . . . . . . tested to jesd78 thermal resistance (typical) ja (c/w) jc (c/w) 10 ld dfn (notes 7, 8) . . . . . . . . . 50 7 junction temperature range . . . . . . . . . . -55c to +150c storage temperature range . . . . . . . . . . . -55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions gate drive bias supply voltage range vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 7.5v input supply voltage range, v in . . . . . . . . 3v to 30v - v dd operating junction temperature range, t j . . -40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 7. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 8. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v dd = 6.5v, t j = -40c to +125c unless otherwis e noted. typical values are at t a =+25c. boldface limits apply over the operating temperature range, -40c to +125c. parameter conditions min (note 9) typ max (note 9) unit bias current characteristics i dd supply current not switching ? 110 180 a pwm input characteristics pwm input bias current v pwm = 5 v ?5?a v pwm = 0 v ??1a pwm input logic low, v il pwmh or pwml v dd = 6.5v ? ? 1.7 v v dd = 5.0v ? ? 1.4 v pwm input logic high, v ih pwmh or pwml v dd = 6.5v 3.4 ?? v v dd = 5.0v 2.7 ?? v hysteresis pwmh or pwml v dd = 6.5v - 1.1 - v v dd = 5.0v - 0.8 - v minimum pwmh on-time to produce gh pulse, t pwmh,on (note 10) c gh = 0 ? 12 - ns minimum gh on-time pulse, t gh,on (note 11) c gh = 0 ? 14 - ns c gh = 3 nf, v hsel = v bst -20- ns minimum pwmh off-time to produce valid gh pulse, t pwmh,off c gh = 0 ? 17 - ns bootstrap diode characteristics forward voltage (v f ) forward bias current 100 ma ? 0.8 ? v zl1505
5 fn6845.2 november 12, 2010 thermal protection thermal trip point ?150? c thermal reset point ?134? c upper gate driver characteristics driver voltage (v bst ? v sw ) ?6? v high-side driver peak gate drive current (pull-up) (v gh ? v sw ) = 2.5v hsel connected to bst 2.0 3.2 ? a hsel connected to sw 1.0 1.7 - a high-side driver peak gate drive current (pull-down) (v gh ? v sw ) = 2.5v hsel connected to bst 2.0 3.2 ? a hsel connected to sw 1.0 1.6 - a high-side driver pull-up resistance (v bst ? v gh ) = 50mv hsel connected to bst ?0.7 0.9 hsel connected to sw -0.9 1.2 high-side driver pull-down resistance (v gh ? v sw ) = 50mv hsel connected to bst ?0.8 1.1 hsel connected to sw ?1.1 1.5 lower gate driver characteristics driver voltage (v dd ) -6.5- v low-side driver peak gate drive current (pull-up) (v gl - v gng ) = 2.5v lsel connected to vdd 3.0 4.5 ? a lsel connected to gnd 1.5 2.4 - a low-side driver peak gate drive current (pull-down) (v gl ? v gnd ) = 2.5v lsel connected to vdd 3.5 5.4 ? a lsel connected to gnd 1.8 2.8 - a low-side driver pull-up resistance (v dd - v gl ) = 50mv lsel connected to vdd ?0.7 0.9 lsel connected to gnd -1.0 1.3 low-side driver pull-down resistance (v gl ? gnd) = 50mv lsel connected to vdd ?0.5 0.7 lsel connected to gnd -0.7 1.0 switching characteristics gh rise time, t rh c gh = 3nf hsel connected to bst ?5.3 8.5 ns hsel connected to sw -10.5 16.5 ns electrical specifications v dd = 6.5v, t j = -40c to +125c unless otherwis e noted. typical values are at t a =+25c. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter conditions min (note 9) typ max (note 9) unit zl1505
6 fn6845.2 november 12, 2010 gh fall time, t fh c gh = 3nf hsel connected to bst -4.8 7.5 ns hsel connected to sw -9.5 15 ns gl rise time, t rl c gl = 3nf lsel connected to vdd ?4.0 6.0 ns lsel connected to gnd -7.8 12 ns gl fall time, t fl c gl = 3nf lsel connected to vdd -3.0 4.5 ns lsel connected to gnd -5.5 8.5 ns gh turn-on propagation delay, t dhr hsel connected to bst ?30.0? ns hsel connected to sw - 31.5 - ns gh turn-off propagation delay, t dhf hsel connected to bst ?37.5? ns hsel connected to sw - 39.0 - ns gl turn-on propagation delay, t dlr lsel connected to v dd ?26.5? ns lsel connected to gnd - 28.0 - ns gl turn-off propagation delay, t dlf lsel connected to v dd ?30.0? ns lsel connected to gnd - 31.5 - ns notes: 9. parameters with min and/or max limits are 100% tested at +2 5c, unless otherwise specified. temperature limits established by characterization and are not production tested. 10. the minimum pwmh on-time pulse (t pwmh , on ) is specified from vpwm = 2.5v on the rise edge to vpwm = 2.5v on the falling edge. 11. the minimum gh on-time pulse (t gh,on ) is specified at v gh = 2.5v. electrical specifications v dd = 6.5v, t j = -40c to +125c unless otherwis e noted. typical values are at t a =+25c. boldface limits apply over the operating temperature range, -40c to +125c. (continued) parameter conditions min (note 9) typ max (note 9) unit t pwmh,on 10% 2. 5v 2. 5v pwm gh 90% 90% 10% t rh t fh t dlr t dlf 2. 5v 2. 5v t gh,on figure 3. timing diagram zl1505
7 fn6845.2 november 12, 2010 typical performance curves figure 4. ivdd vs vdd with temperature (no switching) figure 5. thermal protection thresholds figure 6. minimum gh on-time, t gh,on (note 12, t a = +25c) figure 7. t gh,on with temperature (note 13, c gh = 0) notes: 12. performance curves with temperature are measured at ambient temperatures (t a ) of +85c, +25c and -25c. 13. t gh,on timing is shown in figure 3. 70 80 90 100 110 120 130 4.5 5 5.5 6 6.5 7 7.5 vdd (v) ivdd (ua) -25 c 25 c 85 c 120 125 130 135 140 145 150 155 4.555.566.577.5 vdd (v) t (c) trising tfalling 8 10 12 14 16 18 20 22 4.5 5 5.5 6 6.5 7 7.5 vdd (v) on-time (ns ) cgh=0 cgh=3nf, hsel=bst cgh=3nf, hsel=sw 8 9 10 11 12 13 14 15 16 4.5 5 5.5 6 6.5 7 7.5 vdd (v) on-time (ns ) -25 c 25 c 85 c zl1505
8 fn6845.2 november 12, 2010 figure 8. minimum pwmh on-time, t pwmh,on (c gh = 0) figure 9. minimum pwmh off-time, t pwmh,off (c gh = 0) figure 10. low-side driver pull-up current (v gl = 2.5v, t a = +25c) figure 11. ls pull-up current with temperature (v gl = 2.5v, lsel = vdd) figure 12. low-side driver pull-down current (v gl = 2.5v, t a = +25c) figure 13. ls pull-down current with temperature (v gl = 2.5v, lsel = vdd) typical performance curves (continued) 2 4 6 8 10 12 14 16 4.555.566.577.5 vdd (v) on-time (ns ) -25 c 25 c 85 c 10 14 18 22 26 30 4.5 5 5.5 6 6.5 7 7.5 vdd (v) off-time (ns) -25 c 25 c 85 c 0.6 1.6 2.6 3.6 4.6 5.6 6.6 4.5 5 5.5 6 6.5 7 7.5 vdd (v) igl (a) lsel=vdd lsel=gnd 1.6 2.6 3.6 4.6 5.6 6.6 4.5 5 5.5 6 6.5 7 7.5 vdd (v) igl (a) -25 c 25 c 85 c 1 2 3 4 5 6 7 8 4.5 5 5.5 6 6.5 7 7.5 vdd (v) igl (a) lsel=vdd lsel=gnd 3 4 5 6 7 8 4.555.566.577.5 vdd (v) igl (a) -25 c 25 c 85 c zl1505
9 fn6845.2 november 12, 2010 figure 14. low-side driver rise time, t rl (c gl = 3nf, t a = +25c) figure 15. t rl with temperature (c gl = 3nf, lsel = vdd) figure 16. low-side driver fall time, t fl (c gl =3nf, t a = +25c) figure 17. t fl with temperature (c gl = 3nf, lsel = vdd) figure 18. high-side driver pull-up current (v gh - v sw = 2.5v, t a = +25c) figure 19. hs pull-up current with temperature (v gh - v sw = 2.5v, hsel = bst) typical performance curves (continued) 3 4 5 6 7 8 9 10 11 12 4.5 5 5.5 6 6.5 7 7.5 vdd (v) trise (ns) lsel=vdd lsel=gnd 3 3.5 4 4.5 5 5.5 6 6.5 4.555.566.577.5 vdd (v) trise (ns) -25 c 25 c 85 c 2 3 4 5 6 7 4.555.566.577.5 vdd (v) tfall (ns) lsel=vdd lsel=gnd 2 2.5 3 3.5 4 4.5 4.5 5 5.5 6 6.5 7 7.5 vdd (v) tfall (ns) -25 c 25 c 85 c 0 1 2 3 4 5 4.555.566.577.5 vdd (v) igh (a) hsel=bst hsel=sw 1 1.5 2 2.5 3 3.5 4 4.5 5 4.5 5 5.5 6 6.5 7 7.5 vdd (v) igh (a) -25 c 25 c 85 c zl1505
10 fn6845.2 november 12, 2010 figure 20. high-side driver pull-down current (v gh - v sw = 2.5v, t a =+25c) figure 21. hs pull-down current with temperature (v gh - v sw = 2.5v, hsel = bst) figure 22. high-side driver rise time, t rh (c gh = 3nf, t a = +25c) figure 23. t rh with temperature (c gh = 3nf, hsel = bst) figure 24. high-side driver fall time, t fh (c gh = 3nf, t a = +25c) figure 25. t fh with temperature (c gh = 3nf, hsel = bst) typical performance curves (continued) 0 1 2 3 4 5 4.5 5 5.5 6 6.5 7 7.5 vdd (v) igh (a) hsel=bst hsel=sw 1.5 2 2.5 3 3.5 4 4.5 5 4.5 5 5.5 6 6.5 7 7.5 vdd (v) igh (a) -25 c 25 c 85 c 3.5 5.5 7.5 9.5 11.5 13.5 15.5 17.5 4.5 5 5.5 6 6.5 7 7.5 vdd (v) trise (ns) hsel=bst hsel=sw 3.5 4.5 5.5 6.5 7.5 8.5 4.555.566.577.5 vdd (v) trise (ns) -25 c 25 c 85 c 3.5 5.5 7.5 9.5 11.5 4.5 5 5.5 6 6.5 7 7.5 vdd (v) tfall (ns) hsel=bst hsel=sw 3.5 4.5 5.5 6.5 7.5 4.5 5 5.5 6 6.5 7 7.5 vdd (v) tfall (ns) -25 c 25 c 85 c zl1505
11 fn6845.2 november 12, 2010 zl1505 overview theory of operation the zl1505 is a synchronous n-channel mosfet driver that is intended for use with zilker labs digital-dc pwm controllers to enable a high-efficiency dc/dc conversion scheme. the patented digital-dc control scheme utilizes a closed-loop algorithm to optimize the dead-time applied between the gate drive signals for the high-side and low-side mosfets. by mo nitoring the duty cycle of the resulting dc/dc converter circuit, this dynamic routine continuously varies the mosfet dead times to optimize conversion efficiency in response to varying circuit conditions. the zl1505?s dual pwm input configuration enables this optimization scheme to be applied while minimizing the complexity within the driver device. please refer to the zl2004 data sheet for details on the dynamic dead-time optimization routine. the zl1505 integrates two powerful gate drivers that have been optimized for step-down dc/dc conversion circuit configurations whose output current can exceed 40a per phase. the zl1505 also integrates a 30v bootstrap schottky diode to minimize the external components and provide a high drive voltage to the high-side driver device. variable gate drive current the zl1505 incorporates an innovative variable drive current scheme that enables the user to optimize the gate drive current levels to the requirements of the external mosfets used over a wide range of operating frequencies. each of the gate drivers incorporates a logic input (hsel and lsel) that allows the user to select the gate drive strength to 50% or 100% of the total rated drive current. with the hsel pin connected to the bst pin, the high-side driver can deliver the full rated gate drive current; with the hsel pin connected to the sw pin, the output current will be limited to 50% of the full rated output capability. with the lsel pin connected to vdd, the low-side driver can deliver the full rated gate drive current; with the lsel pin connected to gnd, the output current will be limited to 50% of the full rated output capability. using hsel and lsel, the zl1505 can be used across a wide range of applications using only a simple pcb layout change. also, the vdd pin is the gate drive bias supply for the external mosfets. vdd can be used to vary the gate drive strength as shown for the low-side driver in figures 9 thru 12 and for the high-side driver in figures 17 thru 20. overlap protection circuit the zl1505 includes an internal watchdog circuit that prevents excessive shoot-through current from occurring in the unlikely event that the pwm converter places both switches in the on position. if the overlap time between the pwmh and pwml pulses exceeds 30ns, the pwmh signal will be forced to the low state until the overlap condition ceases, allowing normal switching operation to continue. start-up requirements during power-up, the zl1505 maintains both gh and gl outputs in the low state while the v in voltage is ramping up. once the v dd supply is within specification, the gh and gl pins may be operated using the pwmh and pwml logic inputs respectively. in the case where the pwm controller is powered from a supply other than the zl1505?s v dd supply, and the pwm controller is powered up first, the pwm controller gate outputs should be kept in low or in high-impedance state until the v dd supply is within specif ication. additionally, if the zl1505 begins its power-down sequence prior to the pwm controller then the pwm controller gate outputs should be set in low or in high-impedance state before the v dd voltage supply drops below its specified range. thermal protection when the junction temperature exceeds +150c the high-side driver output gh is forced to logic low state. the driver output is allowed to switch logic states again once the junction temperature drops below +134c. zl1505
12 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6845.2 november 12, 2010 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: zl1505 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 10/19/10 fn6845.2 ?pwm input logic low, vil? on page 4, ch anged max spec from 2.2v to 1.7v for ?vdd = 6.5v?. removed min/typ specs of 1.7/2 ?pwm input logic low, vil? on page 4, changed max spec from 1.9v to 1.4v for ?vdd = 5.0v?. removed min/typ specs of 1.5/1.7 ?pwm input logic high, vih? on page 4, changed min spec from 2.8v to 3.4v for ?vdd = 6.5v?. removed typ/max specs of 3.1/3.4 ?pwm input logic high, vih? on page 4, changed min spec from 2.2v to 2.7v for ?vdd = 5.0v?. removed typ/max specs of 2.5/2.7 7/9/10 on page 4, electrical specifications table, the parameter ?minimum gh on-time pulse, tgh,on (note 11)?, removed 14 and 20 from max column . in typ column, changed 10 to 14 and 14 to 20. on page 4, electrical specifications table, the parameter ?minimum pwmh on-time to produce gh pulse, tpwmh,on (note 10)?, removed 12 fr om max column. in typ column, changed 8.5 to 12. on page 4, electrical specifications table, th e parameter ?minimum pwmh off-time to produce valid gh pulse, tpwmh,off?, removed 17 from max column. in typ column, changed 13 to 17. replaced pod drawing with updated re visions and changes were as follows: converted to new standards by adding land pa ttern and moving dimensions from table onto drawing 2/14/09 fn6845.1 assigned file number fn6845 to datasheet as this will be the first release with an intersil file number. replaced header and footer with inte rsil header and footer . updated disclaimer information to read ?intersil and it?s subsidiari es including zilker labs, inc.? no changes to datasheet content 12/4/09 fn6845.0 converted to new intersil template. chan ged in abs max ratings ?low-side drive voltage for gl pin? from ?(gnd - 0.3) to (vin + 0.3)? to ?(gnd - 0.3) to (vdd + 0.3)?. removed bullet "adjustable gate drive voltage: 4.5v to 7.5v" and "exposed pad 3mmx3mm dfn-10 package" from features. intersil standard s applied are: added related in formation, updated ordering information with notes that includes msl. u pdated abs max ratings with notes, added esd ratings and latchup, added boldface text in electrical spec table. added pod zl1505
13 fn6845.2 november 12, 2010 zl1505 package outline drawing l10.3x3d 10 lead dual flat no-lead plastic package rev 1, 3/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.015mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 10x 0 . 40 index area c (10 x 0.60) (2.80) ( 8x 0 .50 ) ( 10x 0.25 ) (1.60) 0 . 05 max. c 0 . 00 min. 0 . 2 ref seating plane c 5 0.08 (4x) ( 2.30 ) 3.00 0.15 b c 0.10 m a 1.00 max 2.30 10 see detail "x" 0.10 c 10 x 0.25 4 5 m 0.05 c 1.60 index area b 3.00 a pin 1 6 pin 1 6 1 2.0 ref 8x 0.50 bsc 5 angular: 2.50 compliant to jedec mo-229-weed-3 except exposed pad length 7. (2.30mm).

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